Update RFM95 driver (#709)
This commit is contained in:
Olivier
Henrik Ekblad
+71
-237
@@ -40,20 +40,17 @@
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* RFM95 driver-related log messages, format: [!]SYSTEM:[SUB SYSTEM:]MESSAGE
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* - [!] Exclamation mark is prepended in case of error
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*
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* This section is WIP!
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*
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* |E| SYS | SUB | Message | Comment
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* |-|-------|----------|-----------------------------------|---------------------------------------------------------------------
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* | | RFM95 | INIT | | Initialise RFM95 radio
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* | | RFM95 | RCV | SEND ACK | ACK request received, sending ACK back
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* | | RFM95 | PTC | LEVEL=%d | Set TX power level
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* | | RFM95 | SAC | SEND ACK TO=%d,RSSI=%d | Send ACK to node (TO), RSSI of received message (RSSI)
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* | | RFM95 | ATC | ADJ TXL,cR=%d,tR=%d,TXL=%d | Adjust TX level, current RSSI (cR), target RSSI (tR), TX level (TXL)
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* | | RFM95 | SWR | SEND TO=%d,RETRY=%d | Send message to (TO), NACK retry counter (RETRY)
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* | | RFM95 | SWR | ACK FROM=%d,SEQ=%d,RSSI=%d,SNR=%d | ACK received from node (FROM), seq ID (SEQ), (RSSI), (SNR)
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* |!| RFM95 | SWR | NACK | No ACK received
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*
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* |E| SYS | SUB | Message | Comment
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* |-|-------|-------|-----------------------------------|---------------------------------------------------------------------
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* | | RFM95 | INIT | | Initialise RFM95 radio
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* |!| RFM95 | INIT | SANCHK FAIL | Sanity check failed, check wiring or replace module
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* | | RFM95 | RCV | SEND ACK | ACK request received, sending ACK back
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* | | RFM95 | PTC | LEVEL=%d | Set TX power level
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* | | RFM95 | SAC | SEND ACK TO=%d,RSSI=%d | Send ACK to node (TO), RSSI of received message (RSSI)
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* | | RFM95 | ATC | ADJ TXL,cR=%d,tR=%d,TXL=%d | Adjust TX level, current RSSI (cR), target RSSI (tR), TX level (TXL)
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* | | RFM95 | SWR | SEND TO=%d,RETRY=%d | Send message to (TO), NACK retry counter (RETRY)
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* | | RFM95 | SWR | ACK FROM=%d,SEQ=%d,RSSI=%d,SNR=%d | ACK received from node (FROM), seq ID (SEQ), (RSSI), (SNR)
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* |!| RFM95 | SWR | NACK | No ACK received
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*
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* RFM95 modem configuration
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*
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@@ -75,32 +72,33 @@
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#ifndef _RFM95_h
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#define _RFM95_h
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#include "RFM95registers.h"
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// default PIN assignments, can be overridden
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#if defined(__AVR_ATmega168__) || defined(__AVR_ATmega328P__) || defined(__AVR_ATmega328PB__) || defined(__AVR_ATmega88) || defined(__AVR_ATmega8__) || defined(__AVR_ATmega88__)
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#define RFM95_IRQ_PIN (2)
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#define RFM95_RST_PIN (9)
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#define RFM95_IRQ_PIN (2) //!< RFM95_IRQ_PIN
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#define RFM95_RST_PIN (9) //!< RFM95_RST_PIN
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#elif defined(__AVR_ATmega644P__) || defined(__AVR_ATmega1284P__)
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#define RFM95_IRQ_PIN (2)
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#define RFM95_RST_PIN (9)
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#define RFM95_RST_PIN (9) //!< RFM95_RST_PIN
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#elif defined(__AVR_ATmega32U4__)
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#define RFM95_IRQ_PIN (3)
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#define RFM95_RST_PIN (9)
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#define RFM95_IRQ_PIN (3) //!< RFM95_IRQ_PIN
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#define RFM95_RST_PIN (9) //!< RFM95_RST_PIN
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#elif defined(__arm__)
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#define RFM95_IRQ_PIN (10)
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#define RFM95_RST_PIN (27)
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#define RFM95_IRQ_PIN (10) //!< RFM95_IRQ_PIN
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#define RFM95_RST_PIN (27) //!< RFM95_RST_PIN
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#else
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#define RFM95_IRQ_PIN (2) //!< RFM95_IRQ_PIN
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#define RFM95_RST_PIN (9) //!< RFM95_IRQ_PIN
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#define RFM95_IRQ_PIN (2) //!< RFM95_IRQ_PIN
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#define RFM95_RST_PIN (9) //!< RFM95_RST_PIN
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#endif
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#define RFM95_SPI_CS (SS) //!< RFM95_SPI_CS
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// SPI settings
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#define RFM95_SPI_CS (SS) //!< SPI CS/SS pin
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#if !defined(MY_RFM95_SPI_MAX_SPEED)
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#define MY_RFM95_SPI_MAX_SPEED 4000000 //!< SPI speed
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#define MY_RFM95_SPI_MAX_SPEED (4*1000000ul) //!< Max SPI speed, 4Mhz
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#endif
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#define MY_RFM95_SPI_DATA_ORDER MSBFIRST //!< SPI data order
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#define MY_RFM95_SPI_DATA_MODE SPI_MODE0 //!< SPI mode
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#define MY_RFM95_SPI_DATA_ORDER MSBFIRST //!< SPI data order
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#define MY_RFM95_SPI_DATA_MODE SPI_MODE0 //!< SPI mode
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#if defined (ARDUINO) && !defined (__arm__) && !defined (_SPI)
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@@ -109,17 +107,17 @@
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SoftSPI<MY_SOFT_SPI_MISO_PIN, MY_SOFT_SPI_MOSI_PIN, MY_SOFT_SPI_SCK_PIN, MY_RF24_SPI_DATA_MODE>
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_SPI;
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#else
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#define _SPI SPI
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#define _SPI SPI //!< SPI
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#endif
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#else
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#if defined(__arm__)
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#include <SPI.h>
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#else
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extern HardwareSPI SPI; //!< SPI
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extern HardwareSPI SPI; //!< SPI
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#endif
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#if !defined(_SPI)
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#define _SPI SPI //!< SPI
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#define _SPI SPI //!< SPI
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#endif
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#endif
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@@ -130,37 +128,43 @@ extern HardwareSPI SPI; //!< SPI
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#define RFM95_DEBUG(x,...) //!< Debug null
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#endif
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#define RFM95_FIFO_SIZE (0xFFu) //!< Max number of bytes the LORA Rx/Tx FIFO can hold
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#define RFM95_RX_FIFO_ADDR (0x00u) //!< RX FIFO addr pointer
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#define RFM95_TX_FIFO_ADDR (0x80u) //!< TX FIFO addr pointer
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#define RFM95_MAX_PACKET_LEN (0x40u) //!< This is the maximum number of bytes that can be carried by the LORA
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#define RFM95_PREAMBLE_LENGTH (8u) //!< Preamble length, default=8
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#define RFM95_CAD_TIMEOUT_MS (2*1000ul) //!< channel activity detection timeout
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#define RFM95_FXOSC (32000000.0f) //!< The crystal oscillator frequency of the module
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#define RFM95_FSTEP (RFM95_FXOSC / 524288ul) //!< The Frequency Synthesizer step = RFM95_FXOSC /
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#define RFM95_FIFO_SIZE (0xFFu) //!< Max number of bytes the LORA Rx/Tx FIFO can hold
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#define RFM95_RX_FIFO_ADDR (0x00u) //!< RX FIFO addr pointer
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#define RFM95_TX_FIFO_ADDR (0x80u) //!< TX FIFO addr pointer
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#define RFM95_MAX_PACKET_LEN (0x40u) //!< This is the maximum number of bytes that can be carried by the LORA
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#define RFM95_PREAMBLE_LENGTH (8u) //!< Preamble length, default=8
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#define RFM95_RETRIES (2u) //!< Retries in case of failed transmission
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#define RFM95_RETRY_TIMEOUT_MS (500ul) //!< Timeout for ACK, adjustments needed if modem configuration changed (air time different)
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#define RFM95_CAD_TIMEOUT_MS (2*1000ul) //!< channel activity detection timeout
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#define RFM95_PACKET_HEADER_VERSION (1u) //!< RFM95 packet header version
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#define RFM95_MIN_PACKET_HEADER_VERSION (1u) //!< Minimal RFM95 packet header version
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#define RFM95_RETRIES (2u) //!< Retries in case of failed transmission
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#define RFM95_RETRY_TIMEOUT_MS (500ul) //!< Timeout for ACK, adjustments needed if modem configuration changed (air time different)
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#define RFM95_BIT_ACK_REQUESTED (7u) //!< RFM95 header, controlFlag, bit 7
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#define RFM95_BIT_ACK_RECEIVED (6u) //!< RFM95 header, controlFlag, bit 6
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#define RFM95_BIT_ACK_RSSI_REPORT (5u) //!< RFM95 header, controlFlag, bit 5
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#define RFM95_BROADCAST_ADDRESS (255u) //!< Broadcasting address
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#define RFM95_ATC_TARGET_RANGE_PERCENT (5u) //!< ATC target range +/-%
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#define RFM95_RSSI_OFFSET (137u) //!< RSSI offset
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#define RFM95_TARGET_RSSI (-60) //!< RSSI target
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#define RFM95_RSSI_INVALID (127) //!< RSSI invalid
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#define RFM95_SNR_INVALID (127) //!< SNR invalid
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#define RFM95_PROMISCUOUS (false) //!< RFM95 promiscuous mode
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#define RFM95_getACKRequested(__value) ((bool)bitRead(__value, RFM95_BIT_ACK_REQUESTED)) //!< getACKRequested
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#define RFM95_setACKRequested(__value, __flag) bitWrite(__value, RFM95_BIT_ACK_REQUESTED,__flag) //!< setACKRequested
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#define RFM95_getACKReceived(__value) ((bool)bitRead(__value, RFM95_BIT_ACK_RECEIVED)) //!< getACKReceived
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#define RFM95_setACKReceived(__value, __flag) bitWrite(__value, RFM95_BIT_ACK_RECEIVED,__flag) //!< setACKReceived
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#define RFM95_setACKRSSIReport(__value, __flag) bitWrite(__value, RFM95_BIT_ACK_RSSI_REPORT,__flag) //!< setACKRSSIReport
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#define RFM95_getACKRSSIReport(__value) ((bool)bitRead(__value, RFM95_BIT_ACK_RSSI_REPORT)) //!< getACKRSSIReport
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#define RFM95_FXOSC (32*1000000ul) //!< The crystal oscillator frequency of the module
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#define RFM95_FSTEP (RFM95_FXOSC / 524288ul) //!< The Frequency Synthesizer step = RFM95_FXOSC /
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// helper macros
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#define RFM95_getACKRequested(__value) ((bool)bitRead(__value, RFM95_BIT_ACK_REQUESTED)) //!< getACKRequested
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#define RFM95_setACKRequested(__value, __flag) bitWrite(__value, RFM95_BIT_ACK_REQUESTED,__flag) //!< setACKRequested
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#define RFM95_getACKReceived(__value) ((bool)bitRead(__value, RFM95_BIT_ACK_RECEIVED)) //!< getACKReceived
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#define RFM95_setACKReceived(__value, __flag) bitWrite(__value, RFM95_BIT_ACK_RECEIVED,__flag) //!< setACKReceived
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#define RFM95_setACKRSSIReport(__value, __flag) bitWrite(__value, RFM95_BIT_ACK_RSSI_REPORT,__flag) //!< setACKRSSIReport
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#define RFM95_getACKRSSIReport(__value) ((bool)bitRead(__value, RFM95_BIT_ACK_RSSI_REPORT)) //!< getACKRSSIReport
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#define RFM95_internalToRSSI(__value) ((int16_t)(__value - RFM95_RSSI_OFFSET)) //!< Convert internal RSSI to RSSI
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#define RFM95_RSSItoInternal(__value) ((uint8_t)(__value + RFM95_RSSI_OFFSET)) //!< Convert RSSI to internal RSSI
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#define RFM95_internalToSNR(__value) ((int8_t)(__value / 4)) //!< Convert internal SNR to SNR
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// RFM95 radio configurations: reg_1d, reg_1e, reg_26 (see datasheet)
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#define RFM95_BW125CR45SF128 RFM95_BW_125KHZ | RFM95_CODING_RATE_4_5, RFM95_SPREADING_FACTOR_128CPS | RFM95_RX_PAYLOAD_CRC_ON, RFM95_AGC_AUTO_ON //!< 0x72,0x74,0x04
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@@ -341,11 +345,6 @@ LOCAL bool RFM95_setTxPower(uint8_t powerLevel);
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*/
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LOCAL bool RFM95_sleep(void);
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/**
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* @brief Use the radio's Channel Activity Detect (CAD) function to detect channel activity
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* @return true if channel is in use
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*/
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LOCAL bool RFM95_isChannelActive(void);
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/**
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* @brief RFM95_sendACK
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* @param recipient
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* @param sequenceNumber
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@@ -367,8 +366,8 @@ LOCAL bool RFM95_sendWithRetry(const uint8_t recipient, const void* buffer,
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const uint8_t bufferSize, const uint8_t retries = RFM95_RETRIES,
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const uint32_t retryWaitTime = RFM95_RETRY_TIMEOUT_MS);
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/**
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* @brief RFM95_waitCAD
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* @return True if no channel activity detected
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* @brief Wait until no channel activity detected
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* @return True if no channel activity detected, False if timeout occured
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*/
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LOCAL bool RFM95_waitCAD(void);
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/**
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@@ -391,10 +390,16 @@ LOCAL void RFM95_interruptHandler(void);
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*/
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LOCAL void RFM95_clearRxBuffer(void);
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/**
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* @brief RFM95_getRSSI
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* @return RSSI Signal strength of last packet
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* @brief RFM95_getSendingRSSI
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* @return RSSI Signal strength of last packet received
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*/
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LOCAL int16_t RFM95_getRSSI(void);
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LOCAL int16_t RFM95_getReceivingRSSI(void);
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/**
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* @brief RFM95_getSendingRSSI
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* @return RSSI Signal strength of last packet sent (if ACK and ATC enabled)
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*/
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LOCAL int16_t RFM95_getSendingRSSI(void);
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/**
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* @brief RFM_executeATC
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* @param currentRSSI
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@@ -408,182 +413,11 @@ LOCAL bool RFM95_executeATC(const rfm95_RSSI_t currentRSSI, const rfm95_RSSI_t t
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* @param OnOff True to enable ATC
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*/
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LOCAL void RFM95_ATCmode(const bool OnOff, const int16_t targetRSSI = RFM95_TARGET_RSSI);
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volatile rfm95_internal_t RFM95; //!< internal variables
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// Register access
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#define RFM95_READ_REGISTER (0x7Fu) //!< reading register
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#define RFM95_WRITE_REGISTER (0x80u) //!< writing register
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// Registers, available LoRa mode
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#define RFM95_REG_00_FIFO 0x00 //!< REG_00_FIFO
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#define RFM95_REG_01_OP_MODE 0x01 //!< REG_01_OP_MODE
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#define RFM95_REG_02_RESERVED 0x02 //!< REG_02_RESERVED
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#define RFM95_REG_03_RESERVED 0x03 //!< REG_03_RESERVED
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#define RFM95_REG_04_RESERVED 0x04 //!< REG_04_RESERVED
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#define RFM95_REG_05_RESERVED 0x05 //!< REG_05_RESERVED
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#define RFM95_REG_06_FRF_MSB 0x06 //!< REG_06_FRF_MSB
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#define RFM95_REG_07_FRF_MID 0x07 //!< REG_07_FRF_MID
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#define RFM95_REG_08_FRF_LSB 0x08 //!< REG_08_FRF_LSB
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#define RFM95_REG_09_PA_CONFIG 0x09 //!< REG_09_PA_CONFIG
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#define RFM95_REG_0A_PA_RAMP 0x0a //!< REG_0A_PA_RAMP
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#define RFM95_REG_0B_OCP 0x0b //!< REG_0B_OCP
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#define RFM95_REG_0C_LNA 0x0c //!< REG_0C_LNA
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#define RFM95_REG_0D_FIFO_ADDR_PTR 0x0d //!< REG_0D_FIFO_ADDR_PTR
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#define RFM95_REG_0E_FIFO_TX_BASE_ADDR 0x0e //!< REG_0E_FIFO_TX_BASE_ADDR
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#define RFM95_REG_0F_FIFO_RX_BASE_ADDR 0x0f //!< REG_0F_FIFO_RX_BASE_ADDR
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#define RFM95_REG_10_FIFO_RX_CURRENT_ADDR 0x10 //!< REG_10_FIFO_RX_CURRENT_ADDR
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#define RFM95_REG_11_IRQ_FLAGS_MASK 0x11 //!< REG_11_IRQ_FLAGS_MASK
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#define RFM95_REG_12_IRQ_FLAGS 0x12 //!< REG_12_IRQ_FLAGS
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#define RFM95_REG_13_RX_NB_BYTES 0x13 //!< REG_13_RX_NB_BYTES
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#define RFM95_REG_14_RX_HEADER_CNT_VALUE_MSB 0x14 //!< REG_14_RX_HEADER_CNT_VALUE_MSB
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#define RFM95_REG_15_RX_HEADER_CNT_VALUE_LSB 0x15 //!< REG_15_RX_HEADER_CNT_VALUE_LSB
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#define RFM95_REG_16_RX_PACKET_CNT_VALUE_MSB 0x16 //!< REG_16_RX_PACKET_CNT_VALUE_MSB
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#define RFM95_REG_17_RX_PACKET_CNT_VALUE_LSB 0x17 //!< REG_17_RX_PACKET_CNT_VALUE_LSB
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#define RFM95_REG_18_MODEM_STAT 0x18 //!< REG_18_MODEM_STAT
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#define RFM95_REG_19_PKT_SNR_VALUE 0x19 //!< REG_19_PKT_SNR_VALUE
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#define RFM95_REG_1A_PKT_RSSI_VALUE 0x1a //!< REG_1A_PKT_RSSI_VALUE
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#define RFM95_REG_1B_RSSI_VALUE 0x1b //!< REG_1B_RSSI_VALUE
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#define RFM95_REG_1C_HOP_CHANNEL 0x1c //!< REG_1C_HOP_CHANNEL
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#define RFM95_REG_1D_MODEM_CONFIG1 0x1d //!< REG_1D_MODEM_CONFIG1
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#define RFM95_REG_1E_MODEM_CONFIG2 0x1e //!< REG_1E_MODEM_CONFIG2
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#define RFM95_REG_1F_SYMB_TIMEOUT_LSB 0x1f //!< REG_1F_SYMB_TIMEOUT_LSB
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#define RFM95_REG_20_PREAMBLE_MSB 0x20 //!< REG_20_PREAMBLE_MSB
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#define RFM95_REG_21_PREAMBLE_LSB 0x21 //!< REG_21_PREAMBLE_LSB
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#define RFM95_REG_22_PAYLOAD_LENGTH 0x22 //!< REG_22_PAYLOAD_LENGTH
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#define RFM95_REG_23_MAX_PAYLOAD_LENGTH 0x23 //!< REG_23_MAX_PAYLOAD_LENGTH
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#define RFM95_REG_24_HOP_PERIOD 0x24 //!< REG_24_HOP_PERIOD
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#define RFM95_REG_25_FIFO_RX_BYTE_ADDR 0x25 //!< REG_25_FIFO_RX_BYTE_ADDR
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#define RFM95_REG_26_MODEM_CONFIG3 0x26 //!< REG_26_MODEM_CONFIG3
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// Reserved when in LoRa mode
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#define RFM95_REG_40_DIO_MAPPING1 0x40 //!< REG_40_DIO_MAPPING1
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#define RFM95_REG_41_DIO_MAPPING2 0x41 //!< REG_41_DIO_MAPPING2
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#define RFM95_REG_42_VERSION 0x42 //!< REG_42_VERSION
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#define RFM95_REG_4B_TCXO 0x4b //!< REG_4B_TCXO
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#define RFM95_REG_4D_PA_DAC 0x4d //!< REG_4D_PA_DAC
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#define RFM95_REG_5B_FORMER_TEMP 0x5b //!< REG_5B_FORMER_TEMP
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#define RFM95_REG_61_AGC_REF 0x61 //!< REG_61_AGC_REF
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#define RFM95_REG_62_AGC_THRESH1 0x62 //!< REG_62_AGC_THRESH1
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#define RFM95_REG_63_AGC_THRESH2 0x63 //!< REG_63_AGC_THRESH2
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#define RFM95_REG_64_AGC_THRESH3 0x64 //!< REG_64_AGC_THRESH3
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// RFM95_REG_01_OP_MODE 0x01
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#define RFM95_LONG_RANGE_MODE 0x80 //!< LONG_RANGE_MODE
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#define RFM95_ACCESS_SHARED_REG 0x40 //!< ACCESS_SHARED_REG
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#define RFM95_MODE_SLEEP 0x00 //!< MODE_SLEEP
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#define RFM95_MODE_STDBY 0x01 //!< MODE_STDBY
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#define RFM95_MODE_FSTX 0x02 //!< MODE_FSTX
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#define RFM95_MODE_TX 0x03 //!< MODE_TX
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#define RFM95_MODE_FSRX 0x04 //!< MODE_FSRX
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#define RFM95_MODE_RXCONTINUOUS 0x05 //!< MODE_RXCONTINUOUS
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#define RFM95_MODE_RXSINGLE 0x06 //!< MODE_RXSINGLE
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#define RFM95_MODE_CAD 0x07 //!< MODE_CAD
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// RFM95_REG_09_PA_CONFIG 0x09
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#define RFM95_OUTPUT_POWER 0x0F //!< OUTPUT_POWER
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#define RFM95_MAX_POWER 0x70 //!< MAX_POWER
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#define RFM95_PA_SELECT 0x80 //!< PA_SELECT
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// RFM95_REG_0A_PA_RAMP 0x0a
|
||||
#define RFM95_PA_RAMP_3_4MS 0x00 //!< PA_RAMP_3_4MS
|
||||
#define RFM95_PA_RAMP_2MS 0x01 //!< PA_RAMP_2MS
|
||||
#define RFM95_PA_RAMP_1MS 0x02 //!< PA_RAMP_1MS
|
||||
#define RFM95_PA_RAMP_500US 0x03 //!< PA_RAMP_500US
|
||||
#define RFM95_PA_RAMP_250US 0x04 //!< PA_RAMP_250US
|
||||
#define RFM95_PA_RAMP_125US 0x05 //!< PA_RAMP_125US
|
||||
#define RFM95_PA_RAMP_100US 0x06 //!< PA_RAMP_100US
|
||||
#define RFM95_PA_RAMP_62US 0x07 //!< PA_RAMP_62US
|
||||
#define RFM95_PA_RAMP_50US 0x08 //!< PA_RAMP_50US
|
||||
#define RFM95_PA_RAMP_40US 0x09 //!< PA_RAMP_40US
|
||||
#define RFM95_PA_RAMP_31US 0x0A //!< PA_RAMP_31US
|
||||
#define RFM95_PA_RAMP_25US 0x0B //!< PA_RAMP_25US
|
||||
#define RFM95_PA_RAMP_20US 0x0C //!< PA_RAMP_20US
|
||||
#define RFM95_PA_RAMP_15US 0x0D //!< PA_RAMP_15US
|
||||
#define RFM95_PA_RAMP_12US 0x0E //!< PA_RAMP_12US
|
||||
#define RFM95_PA_RAMP_10US 0x0F //!< PA_RAMP_10US
|
||||
#define RFM95_LOW_PN_TX_PLL_OFF 0x10 //!<LOW_PN_TX_PLL_OFF
|
||||
|
||||
// RFM95_REG_0B_OCP 0x0b
|
||||
#define RFM95_OCP_TRIM 0x1f //!< OCP_TRIM
|
||||
#define RFM95_OCP_ON 0x20 //!< OCP_ON
|
||||
|
||||
// RFM95_REG_0C_LNA 0x0c
|
||||
#define RFM95_LNA_BOOST_DEFAULT 0x20 //!< LNA_BOOST_DEFAULT
|
||||
#define RFM95_LNA_BOOST 0x03 //!< LNA_BOOST
|
||||
|
||||
// RFM95_REG_11_IRQ_FLAGS_MASK 0x11
|
||||
#define RFM95_CAD_DETECTED_MASK 0x01 //!< CAD_DETECTED_MASK
|
||||
#define RFM95_FHSS_CHANGE_CHANNEL_MASK 0x02 //!< FHSS_CHANGE_CHANNEL_MASK
|
||||
#define RFM95_CAD_DONE_MASK 0x04 //!< CAD_DONE_MASK
|
||||
#define RFM95_TX_DONE_MASK 0x08 //!< TX_DONE_MASK
|
||||
#define RFM95_VALID_HEADER_MASK 0x10 //!< VALID_HEADER_MASK
|
||||
#define RFM95_PAYLOAD_CRC_ERROR_MASK 0x20 //!< PAYLOAD_CRC_ERROR_MASK
|
||||
#define RFM95_RX_DONE_MASK 0x40 //!< RX_DONE_MASK
|
||||
#define RFM95_RX_TIMEOUT_MASK 0x80 //!< RX_TIMEOUT_MASK
|
||||
|
||||
// RFM95_REG_12_IRQ_FLAGS 0x12
|
||||
#define RFM95_CAD_DETECTED 0x01 //!< CAD_DETECTED
|
||||
#define RFM95_FHSS_CHANGE_CHANNEL 0x02 //!< FHSS_CHANGE_CHANNEL
|
||||
#define RFM95_CAD_DONE 0x04 //!< CAD_DONE
|
||||
#define RFM95_TX_DONE 0x08 //!< TX_DONE
|
||||
#define RFM95_VALID_HEADER 0x10 //!< VALID_HEADER
|
||||
#define RFM95_PAYLOAD_CRC_ERROR 0x20 //!< PAYLOAD_CRC_ERROR
|
||||
#define RFM95_RX_DONE 0x40 //!< RX_DONE
|
||||
#define RFM95_RX_TIMEOUT 0x80 //!< RX_TIMEOUT
|
||||
|
||||
// RFM95_REG_18_MODEM_STAT 0x18
|
||||
#define RFM95_MODEM_STATUS_SIGNAL_DETECTED 0x01 //!< MODEM_STATUS_SIGNAL_DETECTED
|
||||
#define RFM95_MODEM_STATUS_SIGNAL_SYNCHRONIZED 0x02 //!< MODEM_STATUS_SIGNAL_SYNCHRONIZED
|
||||
#define RFM95_MODEM_STATUS_RX_ONGOING 0x04 //!< MODEM_STATUS_RX_ONGOING
|
||||
#define RFM95_MODEM_STATUS_HEADER_INFO_VALID 0x08 //!< MODEM_STATUS_HEADER_INFO_VALID
|
||||
#define RFM95_MODEM_STATUS_CLEAR 0x10 //!< MODEM_STATUS_CLEAR
|
||||
|
||||
// RFM95_REG_1C_HOP_CHANNEL 0x1c
|
||||
#define RFM95_RX_PAYLOAD_CRC_IS_ON 0x40 //!< RX_PAYLOAD_CRC_IS_ON
|
||||
#define RFM95_PLL_TIMEOUT 0x80 //!< PLL_TIMEOUT
|
||||
|
||||
// RFM95_REG_1D_MODEM_CONFIG1 0x1d
|
||||
|
||||
#define RFM95_BW_7_8KHZ 0x00 //!< BW_7_8KHZ
|
||||
#define RFM95_BW_10_4KHZ 0x10 //!< BW_10_4KHZ
|
||||
#define RFM95_BW_15_6KHZ 0x20 //!< BW_15_6KHZ
|
||||
#define RFM95_BW_20_8KHZ 0x30 //!< BW_20_8KHZ
|
||||
#define RFM95_BW_31_25KHZ 0x40 //!< BW_31_25KHZ
|
||||
#define RFM95_BW_41_7KHZ 0x50 //!< BW_41_7KHZ
|
||||
#define RFM95_BW_62_5KHZ 0x60 //!< BW_62_5KHZ
|
||||
#define RFM95_BW_125KHZ 0x70 //!< BW_125KHZ
|
||||
#define RFM95_BW_250KHZ 0x80 //!< BW_250KHZ
|
||||
#define RFM95_BW_500KHZ 0x90 //!< BW_500KHZ
|
||||
|
||||
#define RFM95_IMPLICIT_HEADER_MODE_ON 0x01 //!< IMPLICIT_HEADER_MODE_ON
|
||||
#define RFM95_CODING_RATE_4_5 0x02 //!< CODING_RATE_4_5
|
||||
#define RFM95_CODING_RATE_4_6 0x04 //!< CODING_RATE_4_6
|
||||
#define RFM95_CODING_RATE_4_7 0x06 //!< CODING_RATE_4_7
|
||||
#define RFM95_CODING_RATE_4_8 0x08 //!< CODING_RATE_4_8
|
||||
|
||||
// RFM95_REG_1E_MODEM_CONFIG2 0x1e
|
||||
#define RFM95_SPREADING_FACTOR_64CPS 0x60 //!< SPREADING_FACTOR_64CPS, SF6
|
||||
#define RFM95_SPREADING_FACTOR_128CPS 0x70 //!< SPREADING_FACTOR_128CPS, SF7
|
||||
#define RFM95_SPREADING_FACTOR_256CPS 0x80 //!< SPREADING_FACTOR_256CPS, SF8
|
||||
#define RFM95_SPREADING_FACTOR_512CPS 0x90 //!< SPREADING_FACTOR_512CPS, SF9
|
||||
#define RFM95_SPREADING_FACTOR_1024CPS 0xA0 //!< SPREADING_FACTOR_1024CPS, SF10
|
||||
#define RFM95_SPREADING_FACTOR_2048CPS 0xB0 //!< SPREADING_FACTOR_2048CPS, SF11
|
||||
#define RFM95_SPREADING_FACTOR_4096CPS 0xC0 //!< SPREADING_FACTOR_4096CPS, SF12
|
||||
|
||||
#define RFM95_SYM_TIMEOUT_MSB 0x03 //!< SYM_TIMEOUT_MSB
|
||||
#define RFM95_RX_PAYLOAD_CRC_ON 0x04 //!< RX_PAYLOAD_CRC_ON
|
||||
#define RFM95_TX_CONTINUOUS_MOdE 0x08 //!< TX_CONTINUOUS_MODE
|
||||
|
||||
// RFM95_REG_26_MODEM_CONFIG3 0x26
|
||||
#define RFM95_LOW_DATA_RATE_OPTIMIZE 0x08 //!< LOW_DATA_RATE_OPTIMIZE
|
||||
#define RFM95_AGC_AUTO_ON 0x04 //!< AGC_AUTO_ON
|
||||
|
||||
// RFM95_REG_4D_PA_DAC 0x4d
|
||||
#define RFM95_PA_DAC_DISABLE 0x04 //!< PA_DAC_DISABLE
|
||||
#define RFM95_PA_DAC_ENABLE 0x07 //!< PA_DAC_ENABLE
|
||||
|
||||
/**
|
||||
* @brief RFM95_sanityCheck
|
||||
* @return True if sanity check passed
|
||||
*/
|
||||
LOCAL bool RFM95_sanityCheck(void);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
Reference in New Issue
Block a user