Fix RFM95 driver (RPi) (#800)
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Embedded Innovation
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cde5d8f7c3
commit
63b8d935c8
@@ -55,7 +55,7 @@ LOCAL uint8_t RFM95_spiMultiByteTransfer(const uint8_t cmd, uint8_t* buf, uint8_
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*ptx++ = cmd;
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*ptx++ = cmd;
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while (len--) {
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while (len--) {
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if (aReadMode) {
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if (aReadMode) {
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*ptx++ = RF24_NOP;
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*ptx++ = (uint8_t)RFM95_NOP;
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} else {
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} else {
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*ptx++ = *current++;
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*ptx++ = *current++;
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}
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}
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@@ -78,7 +78,7 @@ LOCAL uint8_t RFM95_spiMultiByteTransfer(const uint8_t cmd, uint8_t* buf, uint8_
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status = _SPI.transfer(cmd);
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status = _SPI.transfer(cmd);
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while (len--) {
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while (len--) {
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if (aReadMode) {
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if (aReadMode) {
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status = _SPI.transfer((uint8_t)0x00);
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status = _SPI.transfer((uint8_t)RFM95_NOP);
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if (buf != NULL) {
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if (buf != NULL) {
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*current++ = status;
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*current++ = status;
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}
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}
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@@ -33,6 +33,7 @@
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// Register access
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// Register access
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#define RFM95_READ_REGISTER (0x7Fu) //!< reading register
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#define RFM95_READ_REGISTER (0x7Fu) //!< reading register
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#define RFM95_WRITE_REGISTER (0x80u) //!< writing register
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#define RFM95_WRITE_REGISTER (0x80u) //!< writing register
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#define RFM95_NOP (0x00u) //!< NOP
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// Registers, available in LoRa mode
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// Registers, available in LoRa mode
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#define RFM95_REG_00_FIFO 0x00 //!< REG_00_FIFO
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#define RFM95_REG_00_FIFO 0x00 //!< REG_00_FIFO
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@@ -122,7 +123,7 @@
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#define RFM95_PA_RAMP_15US 0x0D //!< PA_RAMP_15US
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#define RFM95_PA_RAMP_15US 0x0D //!< PA_RAMP_15US
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#define RFM95_PA_RAMP_12US 0x0E //!< PA_RAMP_12US
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#define RFM95_PA_RAMP_12US 0x0E //!< PA_RAMP_12US
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#define RFM95_PA_RAMP_10US 0x0F //!< PA_RAMP_10US
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#define RFM95_PA_RAMP_10US 0x0F //!< PA_RAMP_10US
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#define RFM95_LOW_PN_TX_PLL_OFF 0x10 //!<LOW_PN_TX_PLL_OFF
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#define RFM95_LOW_PN_TX_PLL_OFF 0x10 //!< LOW_PN_TX_PLL_OFF
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// RFM95_REG_0B_OCP 0x0b
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// RFM95_REG_0B_OCP 0x0b
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#define RFM95_OCP_TRIM 0x1f //!< OCP_TRIM
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#define RFM95_OCP_TRIM 0x1f //!< OCP_TRIM
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