From c965f73838383f7d11d15670ddc371f98b5be8b3 Mon Sep 17 00:00:00 2001 From: TMRh20 Date: Tue, 22 Apr 2014 10:15:55 -0600 Subject: [PATCH] FIFO rd change (Thanks Zephyrr), Initial SI24R1 support - Using status register is faster to read TX FIFO status - Zephyrr (GitHub) - Fixed typo on FLUSH_RX cmd - Added support for pwr levels on SI24R1 chips with smaller code --- RF24.cpp | 64 ++++++++++---------------------------------------------- RF24.h | 35 ++++++++++++++++++------------- 2 files changed, 32 insertions(+), 67 deletions(-) diff --git a/RF24.cpp b/RF24.cpp index bb16c95..831ecdf 100644 --- a/RF24.cpp +++ b/RF24.cpp @@ -235,8 +235,7 @@ uint8_t RF24::read_payload(void* buf, uint8_t data_len) uint8_t RF24::flush_rx(void) { - - return spiTrans( FLUSH_TX ); + return spiTrans( FLUSH_RX ); } /****************************************************************************/ @@ -605,7 +604,7 @@ bool RF24::writeBlocking( const void* buf, uint8_t len, uint32_t timeout ) uint32_t timer = millis(); //Get the time that the payload transmission started - while ( (read_register(FIFO_STATUS) & _BV(FIFO_FULL))){ //Blocking only if FIFO is full. This will loop and block until TX is successful + while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or timeout if( get_status() & _BV(MAX_RT)){ //If MAX Retries have been reached reUseTX(); //Set re-transmit and clear the MAX_RT interrupt flag @@ -638,7 +637,7 @@ bool RF24::writeFast( const void* buf, uint8_t len, const bool multicast ) //Return 0 so the user can control the retrys and set a timer or failure counter if required //The radio will auto-clear everything in the FIFO as long as CE remains high - while ( (read_register(FIFO_STATUS) & _BV(FIFO_FULL))){ //Blocking only if FIFO is full. This will loop and block until TX is successful + while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or fail if( get_status() & _BV(MAX_RT)){ //reUseTX(); //Set re-transmit @@ -1018,63 +1017,22 @@ bool RF24::testRPD(void) /****************************************************************************/ -void RF24::setPALevel(rf24_pa_dbm_e level) +void RF24::setPALevel(uint8_t level) { - uint8_t setup = read_register(RF_SETUP) ; - setup &= ~(_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ; - - // switch uses RAM (evil!) - if ( level == RF24_PA_MAX ) - { - setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ; + if(level > 3){ // If invalid level, go to max PA + level = RF24_PA_MAX << 1 + 1; // +1 to support the SI24R1 chip extra bit + }else{ + level = (level << 1) + 1; // Else set level as requested } - else if ( level == RF24_PA_HIGH ) - { - setup |= _BV(RF_PWR_HIGH) ; - } - else if ( level == RF24_PA_LOW ) - { - setup |= _BV(RF_PWR_LOW); - } - else if ( level == RF24_PA_MIN ) - { - // nothing - } - else if ( level == RF24_PA_ERROR ) - { - // On error, go to maximum PA - setup |= (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ; - } - - write_register( RF_SETUP, setup ) ; + write_register( RF_SETUP, level ) ; // Write it to the chip } /****************************************************************************/ -rf24_pa_dbm_e RF24::getPALevel(void) +uint8_t RF24::getPALevel(void) { - rf24_pa_dbm_e result = RF24_PA_ERROR ; - uint8_t power = read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ; - // switch uses RAM (evil!) - if ( power == (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH)) ) - { - result = RF24_PA_MAX ; - } - else if ( power == _BV(RF_PWR_HIGH) ) - { - result = RF24_PA_HIGH ; - } - else if ( power == _BV(RF_PWR_LOW) ) - { - result = RF24_PA_LOW ; - } - else - { - result = RF24_PA_MIN ; - } - - return result ; + return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH))) >> 1 ; } /****************************************************************************/ diff --git a/RF24.h b/RF24.h index b1f8a37..1571113 100644 --- a/RF24.h +++ b/RF24.h @@ -691,25 +691,27 @@ public: void setAutoAck( uint8_t pipe, bool enable ) ; /** - * Set Power Amplifier (PA) level to one of four levels. - * Relative mnemonics have been used to allow for future PA level - * changes. According to 6.5 of the nRF24L01+ specification sheet, - * they translate to: RF24_PA_MIN=-18dBm, RF24_PA_LOW=-12dBm, - * RF24_PA_MED=-6dBM, and RF24_PA_HIGH=0dBm. + * Set Power Amplifier (PA) level to one of four levels: + * RF24_PA_MIN, RF24_PA_LOW, RF24_PA_HIGH and RF24_PA_MAX + * + * The power levels correspond to the following output levels respectively: + * NRF24L01: -18dBm, -12dBm,-6dBM, and 0dBm + * + * SI24R1: -6dBm, 0dBm, 3dBM, and 7dBm. * * @param level Desired PA level. */ - void setPALevel( rf24_pa_dbm_e level ) ; + void setPALevel ( uint8_t level ); /** * Fetches the current PA level. * - * @return Returns a value from the rf24_pa_dbm_e enum describing - * the current PA setting. Please remember, all values represented - * by the enum mnemonics are negative dBm. See setPALevel for - * return value descriptions. + * NRF24L01: -18dBm, -12dBm, -6dBm and 0dBm + * SI24R1: -6dBm, 0dBm, 3dBm, 7dBm + * + * @return Returns values 0 to 3 representing the PA Level. */ - rf24_pa_dbm_e getPALevel( void ) ; + uint8_t getPALevel( void ); /** * Set the transmission data rate @@ -906,6 +908,10 @@ private: */ void toggle_features(void); + /** + * Built in spi transfer function to simplify repeating code repeating code + */ + uint8_t spiTrans(uint8_t cmd); /**@}*/ @@ -1089,7 +1095,7 @@ private: * This chip uses the SPI bus, plus two chip control pins. Remember that pin 10 must still remain an output, or * the SPI hardware will go into 'slave' mode. * - * @section BoardSupport Board Support + * @section Board_Support Board Support * * Most standard Arduino based boards are supported: * - ATMega 328 based boards (Uno, Nano, etc) @@ -1098,8 +1104,9 @@ private: * hardware SS/CSN pins as extended SPI methods are used. * Initial Due support taken from https://github.com/mcrosson/RF24/tree/due * - ATTiny board support added from https://github.com/jscrane/RF24 - * Note: ATTiny support is built into the library. Do not include SPI.h. - * See here for wiring/pin info. + * Note: ATTiny support is built into the library. Do not include SPI.h.
+ * ATTiny 85: D0(pin 5): MISO, D1(pin6) MOSI, D2(pin7) SCK, D3(pin2):CSN/SS, D4(pin3): CE
+ * ATTiny 84: PA6:MISO, PA5:MOSI, PA4:SCK, PA7:CSN/SS, CE as desired
* * @section More More Information *