Nvm fota (#1018)
* New Firmware OTA for NVM/mcuboot (nRF5) - Support for mcuboot (nRF5) - Support for run length encoded data - Support for smaller FIRMWARE_BLOCK_SIZE, if required * Update NVM * New MY_LOCK_MCU for NRF5 * Test with Sensebender GW + Sensebender Micro was successful
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@@ -66,6 +66,31 @@ void hwWriteConfig(int adr, uint8_t value)
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bool hwInit()
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{
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#ifdef MY_LOCK_MCU
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#ifdef NRF51
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// Lock MCU
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if((uint32_t)((NRF_UICR->RBPCONF & UICR_RBPCONF_PALL_Msk) >> UICR_RBPCONF_PALL_Pos) !=
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UICR_RBPCONF_PALL_Enabled) {
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Flash.write((uint32_t *)&NRF_UICR->RBPCONF, (NRF_UICR->RBPCONF & ~UICR_RBPCONF_PALL_Msk));
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hwReboot();
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}
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#else
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// Lock MCU
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if((uint32_t)((NRF_UICR->APPROTECT & UICR_APPROTECT_PALL_Msk) >> UICR_APPROTECT_PALL_Pos) !=
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UICR_APPROTECT_PALL_Enabled) {
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Flash.write((uint32_t *)&NRF_UICR->APPROTECT, (NRF_UICR->APPROTECT & ~UICR_APPROTECT_PALL_Msk));
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hwReboot();
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}
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#endif
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#endif
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#if defined(NRF51) && defined(CONFIG_ENABLE_PINRESET)
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// Enabling reset for NRF51 isn't handled by arduino-nrf5. Enable it, if requested.
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NRF_POWER->RESET = POWER_RESET_RESET_Enabled;
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NRF_POWER->RAMON |= (POWER_RAMON_ONRAM0_RAM0On << POWER_RAMON_ONRAM0_Pos) |
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(POWER_RAMON_ONRAM1_RAM1On << POWER_RAMON_ONRAM1_Pos);
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#endif
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// Clock is manged by sleep modes. Radio depends on HFCLK.
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// Force to start HFCLK
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NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
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