FIFO rd change (Thanks Zephyrr), Initial SI24R1 support
- Using status register is faster to read TX FIFO status - Zephyrr (GitHub) - Fixed typo on FLUSH_RX cmd - Added support for pwr levels on SI24R1 chips with smaller code
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@@ -691,25 +691,27 @@ public:
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void setAutoAck( uint8_t pipe, bool enable ) ;
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/**
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* Set Power Amplifier (PA) level to one of four levels.
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* Relative mnemonics have been used to allow for future PA level
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* changes. According to 6.5 of the nRF24L01+ specification sheet,
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* they translate to: RF24_PA_MIN=-18dBm, RF24_PA_LOW=-12dBm,
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* RF24_PA_MED=-6dBM, and RF24_PA_HIGH=0dBm.
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* Set Power Amplifier (PA) level to one of four levels:
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* RF24_PA_MIN, RF24_PA_LOW, RF24_PA_HIGH and RF24_PA_MAX
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*
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* The power levels correspond to the following output levels respectively:
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* NRF24L01: -18dBm, -12dBm,-6dBM, and 0dBm
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*
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* SI24R1: -6dBm, 0dBm, 3dBM, and 7dBm.
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*
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* @param level Desired PA level.
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*/
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void setPALevel( rf24_pa_dbm_e level ) ;
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void setPALevel ( uint8_t level );
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/**
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* Fetches the current PA level.
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*
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* @return Returns a value from the rf24_pa_dbm_e enum describing
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* the current PA setting. Please remember, all values represented
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* by the enum mnemonics are negative dBm. See setPALevel for
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* return value descriptions.
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* NRF24L01: -18dBm, -12dBm, -6dBm and 0dBm
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* SI24R1: -6dBm, 0dBm, 3dBm, 7dBm
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*
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* @return Returns values 0 to 3 representing the PA Level.
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*/
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rf24_pa_dbm_e getPALevel( void ) ;
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uint8_t getPALevel( void );
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/**
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* Set the transmission data rate
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@@ -906,6 +908,10 @@ private:
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*/
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void toggle_features(void);
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/**
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* Built in spi transfer function to simplify repeating code repeating code
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*/
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uint8_t spiTrans(uint8_t cmd);
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/**@}*/
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@@ -1089,7 +1095,7 @@ private:
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* This chip uses the SPI bus, plus two chip control pins. Remember that pin 10 must still remain an output, or
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* the SPI hardware will go into 'slave' mode.
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*
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* @section BoardSupport Board Support
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* @section Board_Support Board Support
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*
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* Most standard Arduino based boards are supported:
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* - ATMega 328 based boards (Uno, Nano, etc)
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@@ -1098,8 +1104,9 @@ private:
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* hardware SS/CSN pins as extended SPI methods are used.
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* Initial Due support taken from https://github.com/mcrosson/RF24/tree/due
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* - ATTiny board support added from https://github.com/jscrane/RF24
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* Note: ATTiny support is built into the library. Do not include SPI.h.
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* See <a href="http://programmablehardware.blogspot.ca/2013/09/rf24-with-attiny84.html">here </a>for wiring/pin info.
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* Note: ATTiny support is built into the library. Do not include SPI.h. <br>
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* ATTiny 85: D0(pin 5): MISO, D1(pin6) MOSI, D2(pin7) SCK, D3(pin2):CSN/SS, D4(pin3): CE <br>
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* ATTiny 84: PA6:MISO, PA5:MOSI, PA4:SCK, PA7:CSN/SS, CE as desired <br>
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*
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* @section More More Information
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*
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